释义 |
maximum clock frequency (f&-{max})最高时钟频率 The highest rate at which the clock input of a bistable circuit can be driven through its required sequence, while maintaining stable transitions of logic level at the output, with input conditions established that should cause changes of output logic level, in accordance with the specification. 一种最高速率,在该速率下,双稳态电路的时钟输入端可由所需的时序来驱动,且当输入条件, 根据技术规格,应该引起输出逻辑电平发生变化之时,其输出端可保持逻辑电平的稳定转换。 |