| 释义 |
gatelevel simulation
门级模拟;［闸级模拟］
A detailed level of logic simulation that includes timing analyses (both minimum and maximum rise/fall propagation delays) and race analyses (dynamic design rule checking) as well as provision for undefined and high impedance states.
一种精细的逻辑模拟,它包括定时分析(最大及最小上升/下降传输延时)和竞争分析 (动态设计法则检验),也考虑了不确定的和高阻状态的情况。 |